1. Field of the Invention
The present invention relates to programmable logic devices formed in integrated circuit semiconductor chips. More particularly, the invention relates to logic cells which are part of field programmable gate array chips.
2. Description of the Prior Art
Integrated circuits (ICs) have traditionally implemented a single function, or functions that were defined by software programming. However, in either case, the logic architecture that implemented the functionality was fixed during the design of the IC. More recently, integrated circuits have been developed whose logic architecture can be changed after manufacture. For example, Field Programmable Gate Arrays (FPGAs) have been developed whose logic functions can be established by the user. Typically, the logic functions are implemented in Programmable Function Units (PFUs) which generally includes various logic circuit elements (AND gates, OR gates, NAND gates, NOR gates, flip-flops, lookup table memory, multiplexers, registers, latches, and tri-state buffers, for example) that may be connected in a desired arrangement in order to implement desired logic and memory functions. For example, typical logic functions include combinational logic, adders, counters, and other data path functions. The combinational logic is typically performed using Look-up tables (LUTs), whereas sequential logic is typically performed using storage elements (registers) such as flip-flops and latches.
As mentioned above, each logic cell (or PLC: programmable logic cell) utilizes Look-up Tables (LUTs) to implement combinational logic functions. Typically, LUTs employ Static random access memory's (RAMs) to implement the Boolean functions in accordance with the combinational logic function of each PLC. It is noted, that "K" is to denote the maximum number of inputs which can be coupled to a Boolean network and can be implemented by an individual PLC of an FPGA. Typically, as the value of K increases, the number of levels (e.g., the depth) of LUTs (as well as PLCs) needed to implement application circuits (a circuit implemented in FPGA chip(s)) decrease which, in turn, effects less time delay (e.g., higher circuit speed). Therefore, it is often desirable to have a PLC with a large K value.
For example, FIG. 1 illustrates a prior art block diagram of a LUT 152 of a PLC 150. In particular, LUT 152 is a 16-bit RAM which enables PLC 150 to implement a Boolean function of up to four inputs (e.g., K=4). FIG. 2 illustrates a prior art block diagram of F and GLUTs 162 and 164 of a PLC 160. Both F and G LUTs 162, 164 are 16-bit RAMS enabling PLC 160 to implement a Boolean function of up to Five inputs A1, A2, A3, A4 and A5 (K=5) in correspondence with the circuit configuration of PLC 160 (inputs A2, A3 and A4 are common to both F and G LUTs). FIG. 3 illustrates a block diagram of a FPGA PLC 170 having the respective outputs of the aforementioned F and GLUTs 162 and 164 coupled to an 8-bit H LUT 172 enabling PLC 170 to implement some Boolean functions of up to nine inputs (A1 thru A9) (k=9) in correlation with the circuit configuration of PLC 170.
Therefore, the particular size (RAM) of the LUTs and their circuit configuration in a PLC determine the K value for the particular PLC. For example, the aforementioned PLC 150 (FIG. 2) is provided with 16-bit RAM F and GLUTS 162 and 164 of a combined size of 32 bits providing a K value of five. In contrast, the aforementioned PLC 170 (FIG. 3) has the identical 16-bit RAM F and GLUTS of a combined size of 32 bits providing a K value of eight (since the inputs (A1 to A4 and A6 to A9) of F and GLUTS were independent of one another). Further, an extra LUT may be added to the output terminals of F and GLUTS 162 and 164 in order to raise the K value. For example, the added H-LUT 172 in the PLC 170 (FIG. 3) functioned to increase the value of K by one. However, adding additional LUTS to a PLC increases signal propagation time (e.g., decreases the circuit speed), which is disadvantageous for most circuit applications. Further, an increase in the number of PLC levels in a FPGA correspondingly increases both the size and cost of the FPGA.